Efficient Cache Locking at Private First-Level Caches and Shared Last-Level Cache for Modern Multicore Systems

Most modern computing systems are having multicore processors with multilevel caches for high performance. Caches increase total power consumption and worsen execution time unpredictability. Studies show that way (or partial) cache locking may improve timing predictability and performance-to-power ratio for both single-core and multicore systems. Even though both private first-level and shared last-level cache locking improve timing predictability, it is difficult to justify the performance and power trade-off between these two locking mechanisms. In this work, we evaluate two cache locking schemes for multicore systems – at private first-level caches and at shared last-level cache. Both schemes are based on the analysis of applications’ worst case execution time (WCET) and both allow changing the locked cache size during runtime to achieve the optimal performance-to-power ratio for the running applications. Using Heptane WCET analyser, we generate workloads for H.264/AVC, MPEG4, FFT, MI, and DFT codes. Using VisualSim tool, we model and simulate a system with four cores and two levels of caches. Experimental results confirm that both cache locking schemes improve timing predictability by decreasing the total number of cache misses. Results also indicate that for small applications like FFT, shared last-level cache locking outperforms private first-level cache locking; but for large applications like MPEG4 and H.264/AVC, private first-level cache locking performs better than shared last-level cache locking. Keywords—Cache locking, multicore architecture, performance-to-power ratio, timing predictability, private first-level cache, shared last-cache